A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.