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US08879306B2 Magnetic memory circuit with stress inducing layer 有权
具有应力诱导层的磁记忆电路

Magnetic memory circuit with stress inducing layer
Abstract:
Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.
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