Invention Grant
- Patent Title: Magnetic memory circuit with stress inducing layer
- Patent Title (中): 具有应力诱导层的磁记忆电路
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Application No.: US13208577Application Date: 2011-08-12
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Publication No.: US08879306B2Publication Date: 2014-11-04
- Inventor: Krishnakumar Mani
- Applicant: Krishnakumar Mani
- Applicant Address: US DE Wilmington
- Assignee: III Holdings 1, LLC
- Current Assignee: III Holdings 1, LLC
- Current Assignee Address: US DE Wilmington
- Agency: McAndrews, Held & Malloy, Ltd.
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.
Public/Granted literature
- US20140254250A1 MAGNETIC MEMORY CIRCUIT WITH STRESS INDUCING LAYER Public/Granted day:2014-09-11
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