Invention Grant
- Patent Title: Alignment circuit and receiving apparatus
- Patent Title (中): 对准电路和接收装置
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Application No.: US13726074Application Date: 2012-12-22
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Publication No.: US08879548B2Publication Date: 2014-11-04
- Inventor: Akihiro Nozaki
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2011-281916 20111222
- Main IPC: H04L12/50
- IPC: H04L12/50 ; H04L12/54 ; H04L12/863 ; H04L12/801 ; H04L12/861

Abstract:
A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.
Public/Granted literature
- US20130163599A1 ALIGNMENT CIRCUIT AND RECEIVING APPARATUS Public/Granted day:2013-06-27
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