Invention Grant
- Patent Title: Analyzing a patterning process using a model of yield
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Application No.: US13352713Application Date: 2012-01-18
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Publication No.: US08880382B2Publication Date: 2014-11-04
- Inventor: Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
- Applicant: Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Main IPC: G06G7/48
- IPC: G06G7/48

Abstract:
Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
Public/Granted literature
- US20130185045A1 ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD Public/Granted day:2013-07-18
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