A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters.