A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.