An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.