A tool for rewriting hardware design hardware design language (HDL) code is arranged for receiving HDL code (2) expressing a hardware design of a digital circuit. The tool comprises means (4) for generating a representation (6) of the syntax of the received HDL code, the representation containing a plurality of nodes. The tool further comprises means (3) for determining modifications to the representation of the syntax whereby at least one node is added to or removed from the representation and computation means (9) for generating a modified version (10) of the received HDL code using the received HDL code and modifications to the received HDL code, the modifications determined from the modified representation of the syntax.