Invention Grant
- Patent Title: FEC decoder dynamic power optimization
- Patent Title (中): FEC解码器动态功率优化
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Application No.: US13719893Application Date: 2012-12-19
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Publication No.: US08881082B2Publication Date: 2014-11-04
- Inventor: Vinay Adavani
- Applicant: Vinay Adavani
- Applicant Address: US CA Sunnyvale
- Assignee: Infinera Corporation
- Current Assignee: Infinera Corporation
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity & Harrity LLP
- Agent David L. Soltz
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F15/177 ; G06F9/24

Abstract:
A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace, within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity; and output a new logic gate design based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, producing a same output as the application specific integrated circuit with the logic gate design, based on same inputs.
Public/Granted literature
- US20140173538A1 FEC DECODER DYNAMIC POWER OPTIMIZATION Public/Granted day:2014-06-19
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