Invention Grant
- Patent Title: Method for fabrication of an integrated circuit in a technology reduced with respect to a native technology, and corresponding integrated circuit
- Patent Title (中): 用于制造相对于本机技术减少的技术的集成电路的方法和相应的集成电路
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Application No.: US13618085Application Date: 2012-09-14
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Publication No.: US08881090B2Publication Date: 2014-11-04
- Inventor: Guilhem Bouton , Virginie Bidal
- Applicant: Guilhem Bouton , Virginie Bidal
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: FR1250506 20120118
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
The technological fabrication of the integrated circuit includes a fabrication of the integrated circuit in a reduced technological version of a native technology including at least a first dimensional compensation applied to the reduced channel length and to the reduced channel width of each transistor originating from a transistor, referred to as a “minimum transistor”, designed in the native technology and having in this native technology an initial channel length equal to a minimum length for the native technology and an initial channel width equal to a minimum width for the native technology. The fabrication obtains a transistor having a channel length equal, to a given precision, to the initial channel length and a channel width equal, to a given precision, to the initial channel width.
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