A memory circuit is included. The memory circuit includes n field-effect transistors (n is a natural number of 2 or more) and n capacitors each including a pair of electrodes. A digital data signal is input to one of a source and a drain of the first field-effect transistor. One of a source and a drain of the k-th field-effect transistor (k is a natural number of greater than or equal to 2 and less than or equal to n) is electrically connected to the other of a source and a drain of the (k−1)-th field-effect transistor. One of the pair of electrodes of the m-th capacitor (m is a natural number of n or less) is electrically connected to the other of a source and a drain of the m-th field-effect transistor of the n field-effect transistors. At least two of the n capacitors have different capacitance values.