A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.