Invention Grant
- Patent Title: Processor switchable between test and debug modes
- Patent Title (中): 处理器可在测试和调试模式之间切换
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Application No.: US13650141Application Date: 2012-10-12
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Publication No.: US08887017B2Publication Date: 2014-11-11
- Inventor: Akshay K. Pathak , Rakesh Pandey
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.
Public/Granted literature
- US20140108876A1 PROCESSOR SWITCHABLE BETWEEN TEST AND DEBUG MODES Public/Granted day:2014-04-17
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