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US08891215B2 High noise immunity with latch-up free ESD clamp 有权
高抗噪声,具有无闩锁的ESD钳位

High noise immunity with latch-up free ESD clamp
Abstract:
A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.
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