Invention Grant
- Patent Title: Data bus efficiency via cache line usurpation
- Patent Title (中): 数据总线效率通过缓存线篡夺
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Application No.: US11966900Application Date: 2007-12-28
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Publication No.: US08892823B2Publication Date: 2014-11-18
- Inventor: Steven Gerard LeMire , Vuong Cao Nguyen
- Applicant: Steven Gerard LeMire , Vuong Cao Nguyen
- Applicant Address: US CA Costa Mesa
- Assignee: Emulex Corporation
- Current Assignee: Emulex Corporation
- Current Assignee Address: US CA Costa Mesa
- Agency: McAndrews, Held & Malloy, Ltd.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08

Abstract:
Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
Public/Granted literature
- US20090172287A1 DATA BUS EFFICIENCY VIA CACHE LINE USURPATION Public/Granted day:2009-07-02
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