Invention Grant
US08892837B2 Integrated circuit with tamper-detection and self-erase mechanisms
有权
具有篡改检测和自擦除机制的集成电路
- Patent Title: Integrated circuit with tamper-detection and self-erase mechanisms
- Patent Title (中): 具有篡改检测和自擦除机制的集成电路
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Application No.: US13031804Application Date: 2011-02-22
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Publication No.: US08892837B2Publication Date: 2014-11-18
- Inventor: Noor Hazlina Ramly , Yin Mei Yap
- Applicant: Noor Hazlina Ramly , Yin Mei Yap
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble, Carlyle, Sandridge & Rice
- Main IPC: G06F12/14
- IPC: G06F12/14 ; G06F21/87

Abstract:
Methods and apparatuses for improving security of an integrated circuit (IC) are provided. A tamper condition is detected and a digital key stored in the IC is erased. The digital key is associated with a first image loaded onto the IC from a first memory. The memory may be a non-volatile memory module. A second image is loaded into a second memory module. The second memory module may be an embedded memory module, e.g., a control random access memory (CRAM) module. The first image is then erased from the first and second memory modules.
Public/Granted literature
- US20120216001A1 INTEGRATED CIRCUIT WITH TAMPER-DETECTION AND SELF-ERASE MECHANISMS Public/Granted day:2012-08-23
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