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US08892837B2 Integrated circuit with tamper-detection and self-erase mechanisms 有权
具有篡改检测和自擦除机制的集成电路

Integrated circuit with tamper-detection and self-erase mechanisms
Abstract:
Methods and apparatuses for improving security of an integrated circuit (IC) are provided. A tamper condition is detected and a digital key stored in the IC is erased. The digital key is associated with a first image loaded onto the IC from a first memory. The memory may be a non-volatile memory module. A second image is loaded into a second memory module. The second memory module may be an embedded memory module, e.g., a control random access memory (CRAM) module. The first image is then erased from the first and second memory modules.
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