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US08898597B2 Etch failure prediction based on wafer resist top loss 有权
基于晶圆抗蚀剂顶部损耗的蚀刻失效预测

Etch failure prediction based on wafer resist top loss
Abstract:
An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.
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