Invention Grant
- Patent Title: Coalesced nanowire structures with interstitial voids and method for manufacturing the same
- Patent Title (中): 具有间隙空隙的聚结纳米线结构及其制造方法
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Application No.: US13705792Application Date: 2012-12-05
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Publication No.: US08901534B2Publication Date: 2014-12-02
- Inventor: Patrik Svensson
- Applicant: GLO AB
- Applicant Address: SE Lund
- Assignee: GLO AB
- Current Assignee: GLO AB
- Current Assignee Address: SE Lund
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L33/24
- IPC: H01L33/24 ; H01L29/41 ; H01L29/06 ; H01L33/06 ; H01L33/00 ; H01L33/18 ; H01L33/08

Abstract:
A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.
Public/Granted literature
- US20130092899A1 COALESCED NANOWIRE STRUCTURES WITH INTERSTITIAL VOIDS AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2013-04-18
Information query
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