Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US14174494Application Date: 2014-02-06
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Publication No.: US08901567B2Publication Date: 2014-12-02
- Inventor: Toshihiko Saito
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Robinson Intellectual Proprty Law Office, P.C.
- Agent Eric J. Robinson
- Priority: JP2005-160343 20050531
- Main IPC: H01L29/04
- IPC: H01L29/04 ; H01L27/28 ; G11C5/02 ; G11C8/08 ; H01L27/105 ; H01L27/12 ; H01L49/02

Abstract:
An object of the invention is to reduce an area occupied by a capacitor in a circuit in a semiconductor device, and to downsize a semiconductor device on which the capacitor and an organic memory are mounted. The organic memory and the capacitor, included in a peripheral circuit, in which the same material as the layer containing the organic compound used for the organic memory is used as a dielectric, are used. The peripheral circuit here means a circuit having at least a capacitor such as a resonance circuit, a power supply circuit, a boosting circuit, a DA converter, or a protective circuit. Further, a capacitor in which a semiconductor is used as a dielectric may be provided over the same substrate as well as the capacitor in which the same material as the layer containing the organic compound is used as a dielectric. In this case, it is desirable that the capacitor in which the same material as the layer containing the organic compound is used as a dielectric and the capacitor in which the semiconductor is used as a dielectric are connected to each other in parallel.
Public/Granted literature
- US20140151675A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2014-06-05
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