Invention Grant
- Patent Title: Methods of making JFET devices with pin gate stacks
- Patent Title (中): 制造具有引脚栅极堆叠的JFET器件的方法
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Application No.: US14135281Application Date: 2013-12-19
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Publication No.: US08901625B2Publication Date: 2014-12-02
- Inventor: Chandra Mouli
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder PC
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/808 ; H01L29/10 ; H01L29/80 ; H01L29/15
Abstract:
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
Public/Granted literature
- US20140110753A1 Methods of Making JFET Devices with Pin Gate Stacks Public/Granted day:2014-04-24
Information query
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