Invention Grant
- Patent Title: MOS device with low on-resistance
- Patent Title (中): 具有低导通电阻的MOS器件
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Application No.: US12337059Application Date: 2008-12-17
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Publication No.: US08901648B2Publication Date: 2014-12-02
- Inventor: Sehat Sutardja , Ravishanker Krishnamoorthy
- Applicant: Sehat Sutardja , Ravishanker Krishnamoorthy
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L29/06 ; H01L29/417

Abstract:
Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed.
Public/Granted literature
- US20090250751A1 MOS DEVICE WITH LOW ON-RESISTANCE Public/Granted day:2009-10-08
Information query
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