Invention Grant
- Patent Title: CMOS structures and methods for improving yield
- Patent Title (中): CMOS结构和提高产量的方法
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Application No.: US11757792Application Date: 2007-06-04
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Publication No.: US08901662B2Publication Date: 2014-12-02
- Inventor: Huilong Zhu , Baewon Yang
- Applicant: Huilong Zhu , Baewon Yang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L29/78 ; H01L21/8238
Abstract:
A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.
Public/Granted literature
- US20070252230A1 CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD Public/Granted day:2007-11-01
Information query
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