Invention Grant
- Patent Title: Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same
- Patent Title (中): 具有器件隔离图案的凹陷部分中的无源元件的半导体器件及其制造方法
-
Application No.: US12978669Application Date: 2010-12-27
-
Publication No.: US08901663B2Publication Date: 2014-12-02
- Inventor: Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
- Applicant: Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2010-0080955 20100820
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/82 ; H01L21/28 ; H01L49/02 ; H01L21/8238
Abstract:
A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
Public/Granted literature
Information query
IPC分类:
