Invention Grant
- Patent Title: 3D integration of a MIM capacitor and a resistor
- Patent Title (中): MIM电容和电阻的3D集成
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Application No.: US13126233Application Date: 2009-10-22
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Publication No.: US08901705B2Publication Date: 2014-12-02
- Inventor: Aarnoud Laurens Roest , Mareike Klee , Rudiger Gunter Mauczok , Linda Van Leuken-Peters , Robertus Adrianus Maria Wolters
- Applicant: Aarnoud Laurens Roest , Mareike Klee , Rudiger Gunter Mauczok , Linda Van Leuken-Peters , Robertus Adrianus Maria Wolters
- Applicant Address: NL Eindhoven
- Assignee: NXP, B.V.
- Current Assignee: NXP, B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP08167765 20081028
- International Application: PCT/IB2009/054678 WO 20091022
- International Announcement: WO2010/049859 WO 20100506
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L49/02 ; H01L23/522
Abstract:
The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.
Public/Granted literature
- US20110204480A1 3D INTEGRATION OF A MIM CAPACITOR AND A RESISTOR Public/Granted day:2011-08-25
Information query
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