Invention Grant
US08901724B2 Semiconductor package with embedded die and its methods of fabrication
有权
具有嵌入式芯片的半导体封装及其制造方法
- Patent Title: Semiconductor package with embedded die and its methods of fabrication
- Patent Title (中): 具有嵌入式芯片的半导体封装及其制造方法
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Application No.: US12655335Application Date: 2009-12-29
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Publication No.: US08901724B2Publication Date: 2014-12-02
- Inventor: John Stephen Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K. Nalla
- Applicant: John Stephen Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K. Nalla
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/12 ; H01L23/053 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/498 ; H01L21/56 ; H01L25/03 ; H01L21/683 ; H01L23/538 ; H05K1/18 ; H01L25/10 ; H05K3/46 ; H01L23/00
Abstract:
Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
Public/Granted literature
- US20110215464A1 Semiconductor package with embedded die and its methods of fabrication Public/Granted day:2011-09-08
Information query
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