Invention Grant
- Patent Title: Connector design for packaging integrated circuits
- Patent Title (中): 封装集成电路的连接器设计
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Application No.: US14161111Application Date: 2014-01-22
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Publication No.: US08901735B2Publication Date: 2014-12-02
- Inventor: Chen-Hua Yu , Ying Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Jing-Cheng Lin , Shang-Yun Hou , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/02 ; H01L23/00 ; H01L25/04 ; H01L25/00 ; H01L23/14 ; H01L23/498
Abstract:
A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
Public/Granted literature
- US20140131864A1 Connector Design for Packaging Integrated Circuits Public/Granted day:2014-05-15
Information query
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