A signal processing circuit transfers a signal between an externally connected device and an internal circuit. The signal processing circuit includes a clock selector that selects and outputs any one of clocks received from plural systems; data latch units that respectively latch, according to the respective clocks received from the systems, data pieces being input; a data selector that selects and outputs, among the data pieces latched, a data piece latched according to the selected clock; and a data retaining unit that temporarily retains the data between the data latch units and the internal circuit. When the data is processed between the data retaining unit and the internal circuit, the data retaining unit operates according to an operating clock of the internal circuit, but when the data is processed between the data retaining unit and the data latch units, the data retaining unit operates according to the selected clock.