A dynamic random access memory device may include DRAM memory cells including several lines of memory cells, and line selection circuitry associated with each line. The line selection circuitry may include a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state, and to deliver two intermediate control logic signals each having an intermediate voltage level above the initial level and corresponding to the first logic state. The line selection circuitry may also include a control circuit to be supplied by PMOS transistors with a supply voltage having a second voltage level greater than the intermediate voltage level, and configured to, in the presence of the two intermediate control logic signals have their first logic state deliver to the gates of the memory cell transistors, a selection logic signal having the second voltage level.