Invention Grant
US08904112B2 Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
有权
通过有效地禁用组相关高速缓存的方式来节省功率的方法和装置
- Patent Title: Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
- Patent Title (中): 通过有效地禁用组相关高速缓存的方式来节省功率的方法和装置
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Application No.: US13843885Application Date: 2013-03-15
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Publication No.: US08904112B2Publication Date: 2014-12-02
- Inventor: Martin Licht , Jonathan Combs , Andrew Huang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Mnemoglyphics, LLC
- Agent Lawrence M. Mennemeier
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F1/32 ; G06F9/38 ; G06F12/08

Abstract:
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.
Public/Granted literature
- US20130219205A1 METHOD AND APPARATUS FOR SAVING POWER BY EFFICIENTLY DISABLING WAYS FOR A SET-ASSOCIATIVE CACHE Public/Granted day:2013-08-22
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