Invention Grant
US08904153B2 Vector loads with multiple vector elements from a same cache line in a scattered load operation
有权
在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载
- Patent Title: Vector loads with multiple vector elements from a same cache line in a scattered load operation
- Patent Title (中): 在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载
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Application No.: US12876321Application Date: 2010-09-07
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Publication No.: US08904153B2Publication Date: 2014-12-02
- Inventor: Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
- Applicant: Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen J. Walder, Jr.; William J. Stock
- Main IPC: G06F9/345
- IPC: G06F9/345 ; G06F9/30 ; G06F9/38 ; G06F15/80
Abstract:
Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.
Public/Granted literature
- US20120060015A1 Vector Loads with Multiple Vector Elements from a Same Cache Line in a Scattered Load Operation Public/Granted day:2012-03-08
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