Invention Grant
US08904253B2 Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default
有权
用于测试I / O边界扫描链的方法和设备，默认情况下，I / O的电源关闭
- Patent Title: Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default
- Patent Title (中): 用于测试I / O边界扫描链的方法和设备，默认情况下，I / O的电源关闭
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Application No.: US13532108Application Date: 2012-06-25
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Publication No.: US08904253B2Publication Date: 2014-12-02
- Inventor: Sankaran M. Menon , Robert R. Roeder , Liwei E. Ju
- Applicant: Sankaran M. Menon , Robert R. Roeder , Liwei E. Ju
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Law Office of R. Alan Burnett, P.S
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00 ; G01R31/3185 ; G01R31/319 ; G01R31/317 ; G06F1/32
Abstract:
Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
Public/Granted literature
- US20130346816A1 METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S HAVING I/O'S POWERED OFF BY DEFAULT Public/Granted day:2013-12-26
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