Invention Grant
US08904260B2 Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
有权
用于使用双存储器方案的多级缓存系统中的软错误检测，校正和报告的鲁棒汉明码实现
- Patent Title: Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
- Patent Title (中): 用于使用双存储器方案的多级缓存系统中的软错误检测，校正和报告的鲁棒汉明码实现
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Application No.: US13243370Application Date: 2011-09-23
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Publication No.: US08904260B2Publication Date: 2014-12-02
- Inventor: Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
- Applicant: Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G11C29/00 ; G06F11/10 ; G06F7/483 ; G06F9/30 ; H03M13/35 ; H03M13/29 ; H03K19/00 ; G06F1/32 ; H03K21/00 ; G06F12/02
Abstract:
The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
Public/Granted literature
Information query
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