Invention Grant
- Patent Title: Parameterized cell for planar and finFET technology design
- Patent Title (中): 用于平面和finFET技术设计的参数化单元
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Application No.: US13836057Application Date: 2013-03-15
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Publication No.: US08904324B2Publication Date: 2014-12-02
- Inventor: Navneet Jain , Paul D. Mesa , Qinglei Wang , Qi Xiang , Mahbub Rashed
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Keohane & D'Alessandro, PLLC
- Agent Darrell L. Pogue
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.
Public/Granted literature
- US20140282323A1 PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN Public/Granted day:2014-09-18
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