A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (RC) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in the semiconductor substrate. The semiconductor device design system comprising the at least one processor is also configured to extract parasitic parameters of a coupling in the semiconductor substrate based on the distance determined by the RC extraction tool and a model of the coupling included in a simulation tool.