Invention Grant
- Patent Title: Method for improving resist pattern peeling
- Patent Title (中): 改善抗蚀剂图案剥离的方法
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Application No.: US13666107Application Date: 2012-11-01
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Publication No.: US08906595B2Publication Date: 2014-12-09
- Inventor: Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Chie-Chieh Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G03F7/26
- IPC: G03F7/26 ; G03F1/00

Abstract:
A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
Public/Granted literature
- US20140120459A1 METHOD FOR IMPROVING RESIST PATTERN PEELING Public/Granted day:2014-05-01
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