Invention Grant
- Patent Title: Non-volatile memory (NVM) and logic integration
- Patent Title (中): 非易失性存储器(NVM)和逻辑集成
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Application No.: US13441426Application Date: 2012-04-06
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Publication No.: US08906764B2Publication Date: 2014-12-09
- Inventor: Mehul D. Shroff , Mark D. Hall
- Applicant: Mehul D. Shroff , Mark D. Hall
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Joanna G. Chiu; James L. Clingan, Jr.
- Main IPC: H01L21/8247
- IPC: H01L21/8247

Abstract:
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
Public/Granted literature
- US20130171786A1 NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION Public/Granted day:2013-07-04
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