Invention Grant
- Patent Title: Semiconductor processing methods, and methods of forming isolation structures
- Patent Title (中): 半导体加工方法和形成隔离结构的方法
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Application No.: US13603100Application Date: 2012-09-04
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Publication No.: US08906771B2Publication Date: 2014-12-09
- Inventor: Vladimir Mikhalev , Jim Fulford , Yongjun Jeff Hu , Gordon A. Haller , Lequn Liu
- Applicant: Vladimir Mikhalev , Jim Fulford , Yongjun Jeff Hu , Gordon A. Haller , Lequn Liu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234 ; H01L21/768 ; H01L21/02 ; H01L21/265 ; H01L29/78 ; H01L29/66
Abstract:
Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
Public/Granted literature
- US20120329231A1 Semiconductor Processing Methods, And Methods Of Forming Isolation Structures Public/Granted day:2012-12-27
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