Invention Grant
US08907443B2 Semiconductor device 有权
半导体器件

Semiconductor device
Abstract:
In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection.
Public/Granted literature
Information query
Patent Agency Ranking
0/0