A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating.