A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.