Invention Grant
- Patent Title: Low latency SIMD architecture for iterative decoders
- Patent Title (中): 用于迭代解码器的低延迟SIMD架构
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Application No.: US13336165Application Date: 2011-12-23
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Publication No.: US08908814B2Publication Date: 2014-12-09
- Inventor: Neelmani Kumar , Engling Yeo
- Applicant: Neelmani Kumar , Engling Yeo
- Applicant Address: BB
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB
- Main IPC: H04L27/06
- IPC: H04L27/06 ; H03M13/00 ; H03M13/29

Abstract:
Systems, methods, and other embodiments associated with iterative decoders are described. According to one embodiment, an apparatus includes a set of decoders that are configured to receive data to be decoded. The apparatus may also include a controller configured to separately control each decoder to initiate a decoding sequence based on an occurrence of a transition point. The transition point is a global transition that occurs iteratively for the set of decoders and is based on iterations in a decoding sequence.
Public/Granted literature
- US20120177152A1 LOW LATENCY SIMD ARCHITECTURE FOR ITERATIVE DECODERS Public/Granted day:2012-07-12
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