Invention Grant
US08908814B2 Low latency SIMD architecture for iterative decoders 有权
用于迭代解码器的低延迟SIMD架构

Low latency SIMD architecture for iterative decoders
Abstract:
Systems, methods, and other embodiments associated with iterative decoders are described. According to one embodiment, an apparatus includes a set of decoders that are configured to receive data to be decoded. The apparatus may also include a controller configured to separately control each decoder to initiate a decoding sequence based on an occurrence of a transition point. The transition point is a global transition that occurs iteratively for the set of decoders and is based on iterations in a decoding sequence.
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