Invention Grant
- Patent Title: Cryptographic apparatus and memory system
- Patent Title (中): 加密设备和内存系统
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Application No.: US13037710Application Date: 2011-03-01
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Publication No.: US08908859B2Publication Date: 2014-12-09
- Inventor: Koichi Fujisaki
- Applicant: Koichi Fujisaki
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-211727 20100922
- Main IPC: G06F21/00
- IPC: G06F21/00 ; H04L9/06

Abstract:
According to one embodiment, a cryptographic apparatus includes: cryptographic cores (“cores”), an assigning unit, a concatenating unit, and an output controlling unit. If a CTS flag thereof is on, each core encrypts using a symmetric key cipher algorithm utilizing CTS, while using a symmetric key. When an input of a CTS signal is received, the assigning unit assigns first input data to a predetermined core and turns on the CTS flag thereof. The concatenating unit generates concatenated data by concatenating operation data generated during encrypting the first input data, with second input data that is input immediately thereafter. The output controlling unit controls outputting the concatenated data to the predetermined core, outputting first encrypted data obtained by encrypting the concatenated data, and over outputting second encrypted data obtained by encrypting the first input data, and further turns off the predetermined core's CTS flag.
Public/Granted literature
- US20120069993A1 CRYPTOGRAPHIC APPARATUS AND MEMORY SYSTEM Public/Granted day:2012-03-22
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