Invention Grant
US08909906B2 Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields
有权
分组处理器被配置用于处理具有逻辑运算符和两个特征选择器字段的分支指令指向的特征
- Patent Title: Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields
- Patent Title (中): 分组处理器被配置用于处理具有逻辑运算符和两个特征选择器字段的分支指令指向的特征
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Application No.: US12951591Application Date: 2010-11-22
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Publication No.: US08909906B2Publication Date: 2014-12-09
- Inventor: Hamid Assarpour
- Applicant: Hamid Assarpour
- Applicant Address: US NJ Basking Ridge
- Assignee: Avaya Inc.
- Current Assignee: Avaya Inc.
- Current Assignee Address: US NJ Basking Ridge
- Agency: Anderson Gorecki & Rouille LLP
- Main IPC: G06F9/32
- IPC: G06F9/32 ; H04L12/46 ; H04L12/741
Abstract:
A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a configuration bit vector wherein each bit in the configuration bit vector corresponds to a respective feature. When said branch flag returns a first result processing is continues at an instruction located at a first location relative to a Program Counter (PC) and when the branch flag returns a second result processing is continued at a second location relative to said PC.
Public/Granted literature
- US20110320788A1 METHOD AND APPARATUS FOR BRANCH REDUCTION IN A MULTITHREADED PACKET PROCESSOR Public/Granted day:2011-12-29
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