An SoC is connected to an SDRAM that is controlled by a memory controller and a memory PHY, and the SoC is operable in a normal mode and in a power saving mode. The SoC includes a block A to be powered off in the power saving mode and a block B not to be powered off in the power saving mode. A memory controller is included in the block A. A memory PHY and signal level holding cells are included in the block B. The signal level holding cells are provided between the memory controller and the memory PHY, and are configured to fix output signals from the memory controller at predetermined levels in the power saving mode.