Invention Grant
- Patent Title: Thread synchronization in a multi-thread network communications processor architecture
- Patent Title (中): 线程同步在多线程网络通信处理器架构中
-
Application No.: US12974477Application Date: 2010-12-21
-
Publication No.: US08910171B2Publication Date: 2014-12-09
- Inventor: Deepak Mital , James Clee , Jerry Pirog
- Applicant: Deepak Mital , James Clee , Jerry Pirog
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F9/52
- IPC: G06F9/52 ; G06F15/167 ; G06F9/38 ; G06F9/48 ; H04L12/873

Abstract:
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.
Public/Granted literature
- US20110222552A1 THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE Public/Granted day:2011-09-15
Information query