Invention Grant
- Patent Title: Nonvolatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US13370661Application Date: 2012-02-10
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Publication No.: US08913429B2Publication Date: 2014-12-16
- Inventor: Yasushi Nakajima
- Applicant: Yasushi Nakajima
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-026785 20110210
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/34

Abstract:
According to one embodiment, an erase verification execution unit that makes an erase verify operation of a memory cell, on which an erase operation is performed, to be performed, a number-of-erase-verifications counting unit that counts the number of erase verifications of a memory cell on which the erase operation is performed, and a number-of-erase-verifications setting unit that sets a minimum number of erase verifications for the next time based on the current number of erase verifications counted by the number-of-erase-verifications counting unit are included.
Public/Granted literature
- US20120206965A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2012-08-16
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