Invention Grant
US08914688B2 System and method of reducing test time via address aware BIST circuitry
有权
通过地址感知BIST电路减少测试时间的系统和方法
- Patent Title: System and method of reducing test time via address aware BIST circuitry
- Patent Title (中): 通过地址感知BIST电路减少测试时间的系统和方法
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Application No.: US13685779Application Date: 2012-11-27
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Publication No.: US08914688B2Publication Date: 2014-12-16
- Inventor: George M. Belansek , Kevin W. Gorman , Kiran K. Narayan , Krishnendu Mondal , Michael R. Ouellette
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent David A. Cain, Esq.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/20

Abstract:
In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.
Public/Granted literature
- US20140149810A1 SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY Public/Granted day:2014-05-29
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