Invention Grant
- Patent Title: Circuit for testing integrated circuits
- Patent Title (中): 集成电路测试电路
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Application No.: US12871045Application Date: 2010-08-30
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Publication No.: US08918689B2Publication Date: 2014-12-23
- Inventor: Anirudha Kulkarni , Jasvir Singh
- Applicant: Anirudha Kulkarni , Jasvir Singh
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: IN1682/DEL/2010 20100719
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G01R31/3185 ; G01R31/3187 ; G01R31/319 ; G11C29/12 ; G11C29/32
Abstract:
An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
Public/Granted literature
- US20120017130A1 CIRCUIT FOR TESTING INTEGRATED CIRCUITS Public/Granted day:2012-01-19
Information query
