Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators

Invention Grant

US08927364B2 Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators 有权

Title translation: 具有双应力埋层绝缘体的高性能极薄硅绝缘体互补金属氧化物半导体晶体管的结构和方法

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Patent Title: Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators
Patent Title (中): 具有双应力埋层绝缘体的高性能极薄硅绝缘体互补金属氧化物半导体晶体管的结构和方法
Application No.: US13443133

Application Date: 2012-04-10
Publication No.: US08927364B2

Publication Date: 2015-01-06
Inventor: Ming Cai , Dechao Guo , Liyang Song , Chun-Chen Yeh
Applicant: Ming Cai , Dechao Guo , Liyang Song , Chun-Chen Yeh
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agent Derrick J. Carman
Main IPC: H01L21/8238
IPC: H01L21/8238

Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators

Abstract:

A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

Abstract(Chinese):

一种形成具有n型场效应晶体管（NFET）和具有完全硅化栅电极的p型场效应晶体管（PFET）的互补金属氧化物半导体（CMOS）器件的方法，其中采用改进的双重应力掩埋绝缘体以将NFE和PFET的器件沟道中的机械应力引入和有利。该方法可以施加在体衬底或极薄的绝缘体上（ETSOI）衬底上。该器件包括半导体衬底，在ETSOI层中形成的多个浅沟槽隔离结构，具有源极和漏极区域以及栅极形成的NFET，具有源极和漏极区域的PFET以及栅极形成，绝缘体层，包括沉积在NFET的衬底内的受压氧化物或氮化物，以及沉积在PFET的衬底内的包括应力氧化物或氮化物的第二绝缘体层。

Public/Granted literature

US20130264653A1 STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS Public/Granted day:2013-10-10

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS