According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The memory element stores data in accordance with a change in a resistance state. The non-ohmic element includes a metal layer, a first semiconductor layer containing a first impurity, and a second semiconductor layer which is provided between the first semiconductor layer and the metal layer and which has an unevenly distributed layer.